Jitter – the unwanted timing deviation of a bit or symbol transition – can cause critical errors if it exceeds a certain threshold, and leave frustrated test engineers looking for a solution.
In figure 1, it is clear what jitter does. The green traces have some jitter but the slicer in the center of the eye diagram, will lock in the correct bits. The red traces have excessive jitter and as a result the incorrect bits will be locked in and therefore cause errors.
When combined with amplitude (or signal) noise, limited bandwidth, and multi-level signaling such as PAM4, timing deviations and signal integrity can get exponentially worse, and error-free transmission will be impossible if jitter is not controlled.
Figures 2 through 5 show the combined cumulative effects of noise, limited bandwidth and jitter on a PAM4 signal. Even moderate amounts of jitter can now cause the wrong symbol to be locked in.
Therefore, it is critical to characterize a high-speed interface and determine the margin of operation through jitter, eye opening, TDECQ, and other important measurements that are a figure of merit for the signal quality of a high-speed interface.
Test instrumentation requirements
To be able to properly characterize the quality of the high-speed interface, it is important that the jitter noise floor of the test instrumentation is low enough to be able to measure the jitter of the devices under test.
It’s also important that measurement equipment can track low frequency variations of the embedded clock in the high-speed signal. So-called clock wander is typical in link technologies that rely heavily on digital signal processing at the receiver or other advanced signaling formats.
Consequently, ultra-low jitter noise floor and PLL-based low frequency clock phase tracking are essential to provide the precision measurement conditions necessary for accurate and repeatable characterization of 100G per channel and above HSIO interfaces.
The new QCA Series platform targets applications across ATE testing for switch ASICs, GPUs/CPUs, and AI processing ICs, 100-800G and 1.6T Ethernet, emerging Co-Packaged Optics and In-package Optical I/O, and computer interfaces such as PCI Express and USB.
With ultra-low jitter performance and unrivalled instrument density, it is ideally suited to perform high-precision measurements in parallel for optimized test throughput and reduced cost-of test in high-volume manufacturing applications.
